1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a laminated wiring structure.
2. Description of the Related Art
In recent years, along with expansion of functions and improvement of performance of semiconductor devices, the number of transistors mounted on a chip has been significantly increased while reducing the chip size. As such highly-integrated semiconductor devices with the reduced chip size require more wirings, wiring structures having higher density have been developed.
However, increasing wiring structure density results in an increase of wiring capacity C due to reduction of the distance between wirings, an increase of wiring resistance R due to reduction of the wiring width, and a consequent increase of RC wiring delay.
One solution for these problems is to form wiring structures using a dual damascene process, where Cu wiring is used in order to reduce the wiring resistance R and eventually reduce wiring delay. The dual damascene process is for forming vias as vertical wiring and wiring of wiring layers at the same time. More specifically, the dual damascene process is for forming via holes and wiring grooves, filling the via holes and the wiring grooves with Cu, and flattening the surface of Cu by chemical mechanical polishing (CMP).
For the purpose of reducing wiring capacity, films made of a low dielectric constant material (so-called “low-k films”) are used as interlayer insulation films. The low-k films have a lower dielectric constant than silicon oxide films (SiO2, relative dielectric constant: 4.3) that have been conventionally used as interlayer insulation films. Examples of low-k films include inorganic insulation films of SiOC, porous silica, etc., and organic insulation films of polyimide series and Teflon™ series.
The low-k films not only have a lower relative dielectric constant but also have a lower density than the silicon oxide films. Accordingly, the low-k films easily absorb process gases, etching gases, water, and the like used during film formation, and hold a much larger amount of gas than the silicon oxide films. The gas held in the low-k films expand during the later heat treatment. The expanded gas exerts a very high stress on the low-k films and the wiring layers, and might cause breakage.
TEOS silicon oxide films (hereinafter referred to as “TEOS films”) are used to cover the surface of the low-k films in order to prevent absorption of gases, etc., into the low-k films. The TEOS films are denser than the low-k films, and thus prevent the process gases, etc., from entering the low-k films from the outside.
In the process of forming fine wiring structures in the low-k films, resist films made of chemically amplified photoresist materials are used. For example, in the case of the positive type, when the chemically amplified photoresist materials are exposed to light, acid substances are produced to form latent images. Then, when the acid substances are subjected to heat treatment, the acid substances act on and degrade a dissolution preventing agent so as to render the latent images soluble by an alkaline developer. If low-k films are used as interlayer insulation film, gas contained in the low-k films produces basic substances, which neutralize acid substances present in the latent image area of the resist films. The amount of the acid substances thus becomes too small to act on the dissolution preventing agent, resulting in poor development of the photoresist film, i.e., so-called “resist poisoning” (or simply “poisoning”).
Patent Document 1 discloses a laminated structure having a TEOS film for preventing diffusion of basic substances. According to Patent Document 1, as shown in FIG. 1, a laminated structure 100 includes TEOS films 103 disposed between low-k films 104 and silicon nitride films 102 so as to prevent the low-k films 104 from coming in contact with nitrogen and ammonia gas used for forming the silicon nitride films 102, thereby preventing resist poisoning.
<Patent Document 1> Japanese Patent Laid-Open Publication No. 2004-6627
Generally, TEOS films are formed by vaporizing liquid TEOS as a raw material, and mixing the vaporized TEOS with oxygen (O2) gas serving as an oxidizer, with use of plasma chemical vapor deposition (CVD) devices. In a processing chamber of a typical plasma CVD device, mixed gas of TEOS and O2 gas is ionized by plasma so as to cause a reaction on the surface of a heated wafer. As a result of the reaction, a TEOS film is formed. That is, plasma CVD devices used for forming TEOS films need to have vaporization mechanisms to vaporize liquid TEOS, and therefore have more complex mechanisms than plasma CVD devices that only use gas as a raw material. This means that production of semiconductor devices including such TEOS films requires higher device costs and higher manufacturing costs.